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Features
* Single-chip All-in-one Design, Only Requires External DAC
- MIDI Control Processor, Serial and Parallel Interface - Synthesis, General MIDI Wavetable Implementation - Compatible Effects: Reverb + Chorus - Spatial Effect - 4-band Stereo Equalizer State-of-the-art Synthesis for Best Quality/Price Products - 38-voice Polyphony + Effects - On-chip CleanWaveTM Wavetable Data, Firmware, RAM Delay Lines Synthesizer Chipset: ATSAM2193/ATSAM2193-G + DAC Hardware Programmable DAC Mode - I2S: 16 to 20 bits - Japanese: 16 bits Typical Applications - Battery-operated Musical Keyboards - Portable Phones - Karaokes TQFP44 (10 mm x 10 mm) Package for ATSAM2193 TFBGA44 (7 mm x 7 mm) Package for ATSAM2193-G - Both Options Provide Small Footprint, Low Pin Count Low-power - 95 mW Typical Operating, <5 A Power-down - 2.5V and 3.3V Power Supply or Single 2.5V Supply - Built-in Power Switch
* * * *
Sound Synthesis ATSAM2193 ATSAM2193-G Low-power Single-chip Synthesizer with Effects
* *
Description
The ATSAM2193 provides a single-chip, low-cost MIDI sound system. Equipped with a serial and a parallel MIDI input, it provides state-of-the-art sound synthesis using a full GM sound set together with a range of compatible effects. Its low power consumption makes it ideal for all battery-powered applications such as portable Karaoke or any other device using MIDI synthesis. The ATSAM2193-G has the same functionality as the ATSAM2193 but is presented in a TFBGA44 package. Figure 1. Typical Hardware Configuration
MIDI IN MPU-401 (Parallel MIDI)
ATSAM2193 or ATSAM2193-G
Stereo DAC
Audio Out
Rev. 2695A-DRMSD-06/03
1
Pin Description
44-lead TQFP Package
Table 1. Pin by Function - 44-lead TQFP Package
Pin Name Pin Number Type Function
Power Supply Group GND VC3 VC2 9, 11, 20, 22, 30, 34, 38, 42 10, 29 1, 12, 32, 41, 44 35 PWR PWR PWR Digital ground - all pins should be connected to a ground plane. I/O power supply, 2.25V to 3.6V. All pins should be connected to a nominal 3.3V power. Core power supply, 2.25V to 2.75V. All pins should be connected to nominal 2.5V. If the built-in power switch is used for minimum power-down consumption, then all these pins should be connected to the output of the power switch PWROUT (pin 36). Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin must be connected to nominal 2.5V.
PWRIN
PWR
Serial MIDI, Parallel MIDI (MPU-401) MIDI IN 17 IN Serial TTL MIDI IN. Connected to the built-in synthesizer at power-up or after MPU reset. Connected to the D0 - D7 bus (read mode) when MPU switched to UART mode. This pin should be tied HIGH if not used. 8-bit bi-directional bus, under control of CS, RD, WR. These pins should be left unconnected if not used. This pin has built-in pull-down. Should be left unconnected if not used. Select: 0 = data registers (read/write) 1 = status register (read), control register (write) Chip select, active low. This pin has a built-in pull-down. It should be left unconnected if not used. Read, active low. When CS and RD are low, data (A0 = 0) or status (A0 = 1) is read on D0D7. Read data is acknowledged on the rising edge of RD. This pin has a built-in pull-down. It should be left unconnected if not used. Write, active low. When CS and WR are low, data (A0 = 0) or control (A0 = 1) is written from the D0 -D7 bus to the ATSAM2193 on the rising edge of WR. This pin has a built-in pull-up. It should be left unconnected if not used. A rising edge indicates that a MIDI byte is available for read on D0 - D7. Acknowledged by reading the byte.
D0 - D7 A0
6, 8, 14, 16, 18, 21, 24, 26 2
I/O IN
CS RD
4 31
IN IN
WR
33
IN
IRQ
28
OUT
Digital Audio Group CLBD WSBD DABD DACSEL 3 23 27 15 OUT OUT OUT IN Digital audio bit clock. Digital audio left/right select. Digital audio stereo output. DAC type: 0 = I2S 16 to 20 bits 1 = Japanese 16 bits
Miscellaneous Group X1, X2 39, 40 9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (2.5VPP max through 47 pF capacitor). X2 cannot be used to drive external circuits, use CKOUT instead.
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ATSAM2193/ATSAM2193-G
2695A-DRMSD-06/03
ATSAM2193/ATSAM2193-G
Table 1. Pin by Function - 44-lead TQFP Package (Continued)
Pin Name CKOUT LFT RESET PWROUT PDWN Pin Number 7 43 5 36 37 Type OUT IN PWR IN Function Buffered X2 output, can be used to drive external DAC master clock (256 * Fs) PLL external RC network. Reset input, active low. This is a Schmitt trigger input, allowing direct connection to an RC network. Power switch output. Use this pin to supply 2.5V nominal core voltage by connecting it to all VC2 pins. Power down, active low. When power down is active, all outputs are set to logic level 0. The PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V supply is removed from the core. To exit from power down, PDWN must be set to VC2, then RESET applied. When unused this pin must be connected to VC2. Test pins, should be grounded. When high, indicates synthesizer is up and running.
TEST0 TEST1 RUN
13, 25 19
IN OUT
Table 2. Pinout by Pin Number - 44-lead TQFP Package
Pin Number 1 2 3 4 5 6 7 8 9 10 11 Signal Name VC2 A0 CLBD CS RESET D0 CKOUT D1 GND VC3 GND Pin Number 12 13 14 15 16 17 18 19 20 21 22 Signal Name VC2 TEST0 D2 DACSEL D3 MIDI IN. D4 RUN GND D5 GND Pin Number 23 24 25 26 27 28 29 30 31 32 33 Signal Name WSBD D6 TEST1 D7 DABD IRQ VC3 GND RD VC2 WR Pin Number 34 35 36 37 38 39 40 41 42 43 44 Signal Name GND PWRIN PWROUT PDWN GND X1 X2 VC2 GND LFT VC2
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2695A-DRMSD-06/03
44-ball TFBGA Package
Table 3. Pin by Function - 44-ball TFBGA Package
Pin Name Pin Number Type Function
Power Supply Group GND A4, B4, C3, C5, E3, E5, G2, G6 A7, D1 D6, F2, F4, F7, G5 F1 PWR Digital ground - all pins should be connected to a ground plane.
VC3 VC2
PWR PWR
I/O power supply, 2.25V to 3.6V. All pins should be connected to a nominal 3.3V power. Core power supply, 2.25V to 2.75V. All pins should be connected to nominal 2.5V. If the built-in power switch is used for minimum power-down consumption, then all these pins should be connected to the output of the power switch PWROUT (pin 36). Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this pin must be connected to nominal 2.5V.
PWRIN
PWR
Serial MIDI, Parallel MIDI (MPU-401) MIDI IN B5 IN Serial TTL MIDI IN. Connected to the built-in synthesizer at power-up or after MPU reset. Connected to the D0 - D7 bus (read mode) when MPU switched to UART mode. This pin should be tied HIGH if not used. 8-bit bi-directional bus, under control of CS, RD, WR. These pins should be left unconnected if not used. This pin has built-in pull-down. Should be left unconnected if not used. Select: 0 = data registers (read/write) 1 = status register (read), control register (write) Chip select, active low. This pin has a built-in pull-down. It should be left unconnected if not used. Read, active low. When CS and RD are low, data (A0 = 0) or status (A0 = 1) is read on D0D7. Read data is acknowledged on the rising edge of RD. This pin has a built-in pull-down. It should be left unconnected if not used. Write, active low. When CS and WR are low, data (A0 = 0) or control (A0 = 1) is written from the D0 -D7 bus to the ATSAM2193 on the rising edge of WR. This pin has a built-in pull-up. It should be left unconnected if not used. A rising edge indicates that a MIDI byte is available for read on D0 - D7. Acknowledged by reading the byte.
D0 - D7
D7, C7, B6, A5, B3, A2, B1, C1 F5
I/O
A0
IN
CS RD
E6 E2
IN IN
WR
G1
IN
IRQ
D2
OUT
Digital Audio Group CLBD WSBD DABD DACSEL F6 A1 C2 A6 OUT OUT OUT IN Digital audio bit clock. Digital audio left/right select. Digital audio stereo output. DAC type: 0 = I2S 16 to 20 bits 1 = Japanese 16 bits
Miscellaneous Group X1, X2 G3, G4 9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (2.5VPP max through 47 pF capacitor). X2 cannot be used to drive external circuits, use CKOUT instead.
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ATSAM2193/ATSAM2193-G
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ATSAM2193/ATSAM2193-G
Table 3. Pin by Function - 44-ball TFBGA Package (Continued)
Pin Name CKOUT LFT RESET PWROUT PDWN Pin Number C6 G7 E7 E1 F3 Type OUT IN PWR IN Function Buffered X2 output, can be used to drive external DAC master clock (256 * Fs) PLL external RC network. Reset input, active low. This is a Schmitt trigger input, allowing direct connection to an RC network. Power switch output. Use this pin to supply 2.5V nominal core voltage by connecting it to all VC2 pins. Power down, active low. When power down is active, all outputs are set to logic level 0. The PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V supply is removed from the core. To exit from power down, PDWN must be set to VC2, then RESET applied. When unused this pin must be connected to VC2. Test pins, should be grounded. When high, indicates synthesizer is up and running.
TEST0 TEST1 RUN
B7, B2 A3
IN OUT
Figure 2. Pinout by Pin Coordinate - 44-ball TFBGA (Top View)
WSBD
D5
RUN
GND
D3
DACSEL VC3
D6
TEST1
D4
GND MIDI IN
D2
TEST0
D7
DABD
GND
GND CKOUT
D1
VC3
IRQ
VC2
D0
PWROUT RD
GND
GND
CS
RESET
PWRIN VC2 WR GND
PDWN X1
VC2 X2
A0 VC2
CLBD GND
VC2 LFT
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2695A-DRMSD-06/03
Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings
Ambient Temperature (Power applied) ........... -40C to +85C Storage Temperature ..................................... -65C to +150C Voltage on Input Pins................................. -0.5V to VC3 + 0.3V (except X1 and PDWN) Voltage on X1 and PDWN Pins.................. -0.5V to VC2 + 0.3V VC2 Supply Voltage (core).....................................-0.5V to +3V VC3 Supply Voltage (I/O) ....................................-0.3V to +4.5V Maximum IOL per I/O pin................................................. 4 mA *NOTICE:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 5. Recommended Operating Conditions
Symbol VC2 VC3(1) tA Note: Parameter Supply voltage Supply voltage Operating ambient temperature Min 2.25 2.5 0 Typ 2.5 3.3 Max 2.75 3.6 70 Unit V V C
1. When using 3.3V VCC supply in a 5V environment, care must be taken that pin voltage does not exceed VC3+0.3V. Pin X1 is powered by VC2, therefore voltage on this pin should not exceed VC2+0.3V. VC3 should not be lower than VC2.
DC Characteristics
Table 6. DC Characteristics (tA = 25C, VC2 = 2.5V 10%, VC3 = 3.3V 10%)
Symbol VIL VIH VIL VIH VOL VOH Parameter Low-level input voltage (Except X1, PDWN) High-level input voltage (Except X1, PDWN) Low-level input voltage for X1, PDWN High-level input voltage for X1, PDWN Low-level output voltage IOL = -2mA High-level output voltage IOH = 2mA Power consumption (crystal frequency =9.6 MHz) Power down supply current (using power switch) Min -0.3 2.3 -0.3 2 2.9 Typ 95 1 5 Max 1.0 VC3+0.3 0.3 VC2+0.3 0.4 Unit V V V V V V mW A
6
ATSAM2193/ATSAM2193-G
2695A-DRMSD-06/03
ATSAM2193/ATSAM2193-G
Parallel MPU-401 Interface Timings
Figure 3. MPU Interface Read Cycle
A0 tAVCS CS
tCSLRDL RD
tPRD
tRDHCSH
tRDLDV D0 - D7
tDRH
IRQ
Figure 4. MPU Interface Write Cycle
tWRCYC A0 tAVCS CS
tCSLWRL WR
tPWR
tWRHCSH
tDWS D0 - D7
tDWH
Table 7. MPU Interface Timing Parameters
Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLDV tDRH tCSLRWRL tWRHCSH tPWR tDWS tDWH tWRCYC Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD Chip select low to WR low WR high to CS high WR pulse width Write data setup time Write data hold time Write cycle Min 0 5 5 50 5 5 5 50 10 0 3 Typ Max 20 10 Unit ns ns ns ns ns ns ns ns ns ns ns s
7
2695A-DRMSD-06/03
Digital Audio Timings
Figure 5. Digital Audio
tCW WSBD tCW tCLBD
CLBD tSOD DABD tSOD
Table 8. Digital Audio Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD rising to WSBD change DABD valid prior/after CLBD rising CLBD cycle time Min 200 200 416.67 Typ Max Unit ns ns ns
Figure 6. Digital Audio Frame Format
WSBD (I2S) WSBD (Japanese)
CLBD
DABD
MSB
LSB 16 bits
LSB 18 bits
LSB 20 bits
MSB
Notes:
1. Selection between I2S and Japanese format is via pin DACSEL.
8
ATSAM2193/ATSAM2193-G
2695A-DRMSD-06/03
ATSAM2193/ATSAM2193-G
Reset and Powerdown
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized. This takes about 20 ms. A typical RC/diode power-up network can be used. After RESET, the ATSAM2193 or ATSAM2193-G enters an initialization routine. It takes around 50 ms before a MIDI IN or MPU message can be processed. If PDWN is asserted low, then the crystal oscillator and PLL are stopped. The chip enters a deep power-down sleep mode. To exit power down, PDWN must be asserted high, then RESET applied. Power-down mode is managed by an internal power switch. The equivalent schematic and standard connection is shown in Figure 7. All the VC2 pins must be connected to PWROUT. Figure 7. Schematic
VC2 Source from Power Supply PDWN = L: Power-down Mode (Internal Power Switch Open) PDWN = H: Operating Mode (Internal Power Switch Closed)
PWRIN
PDWN
PWROUT
ATSAM2193 ATSAM2193-G
VC2 VC2 VC2 VC2 VC2 VC2
Note:
High level for PDWN is VC2 = 2.5V 10%.
Figure 8. PDWN Connection Example
3.3V 3.3V 2.5V
VC3
VC3
PWRIN
VC2
PWROUT 10 kOhm PDWN Control (High level = 3.3V) PDWN
HOST
ATSAM2193 ATSAM2193-G
9
2695A-DRMSD-06/03
Recommended Board Layout
Like all HCMOS high integration ICs, the following simple rules of board layout are mandatory for reliable operation: * GND, VC3, VC2 Distribution and Decouplings All GND, VC3, VC2 pins should be connected. A GND plane is strongly recommended below the ATSAM2193 and ATSAM2193-G. The board GND + VC2 distribution should be in grid form. Recommended VC2 decoupling is 0.1 F at each corner of the IC with an additional 10 F between pins 42 and 44 for the ATSAM2193 and between pins G6 and F7 for the ATSAM2193-G. VC3 requires a single 0.1 uF decoupling. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-CR and the device should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from the device. * Analog Section A specific AGND ground plane should be provided, which is connected to the GND ground by a single trace. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the analog section.
10
ATSAM2193/ATSAM2193-G
2695A-DRMSD-06/03
ATSAM2193/ATSAM2193-G
Recommended Crystal Compensation and LFT Filter
Figure 9. ATSAM2193
39 X1 40 43 9.6 MHz C1
22 pF
X1 X2 LFT
C2
1 nF
R1
470 Ohm
C4
22 pF
C3
10 nF
GND
GND
ATSAM2193
GND
Figure 10. ATSAM2193-G
G3 X1 G4 G7 9.6 MHz C4
22 pF
X1 X2 LFT
C2
1 nF
R1
470 Ohm
C1
22 pF
C3
10 nF
GND
GND
ATSAM2193-G
GND
11
2695A-DRMSD-06/03
Mechanical Dimensions
44-lead TQFP Package
Figure 11. Thin Plastic 44-lead Quad Flat Pack (TQFP44)
Table 9. 44-lead TQFP Package Dimensions (in mm)
Parameter A A1 A2 D D1 E E1 L P B 0.3 0.45 0.05 1.35 1.40 12.00 10.00 12.00 10.00 0.60 0.80 0.37 0.45 0.75 Min Nom Max 1.60 0.15 1.45
12
ATSAM2193/ATSAM2193-G
2695A-DRMSD-06/03
ATSAM2193/ATSAM2193-G
44-ball TFBGA Package
Figure 12. 44-ball TFBGA Package
0.80
0.26
0.35
0.53
Figure 13. Package Marking
F RANCE
SAM2193-G YYWW 57541A XXXXXXXXX
Note: A1 Ball in lower left-hand corner.
13
2695A-DRMSD-06/03
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(c) Atmel Corporation 2003. All rights reserved. Atmel (R) and combinations thereof and CleanWave (R) are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper.
2695A-DRMSD-06/03 0M

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